1. Field of the Invention
The present invention relates to semiconductor devices and a method of manufacturing the same, and in particular to semiconductor devices and a method of manufacturing the same contemplating improvement of breakdown voltage and reduction of leakage current.
2. Description of the Background Art
A method of manufacturing a bipolar transistor as an exemplary conventional semiconductor device will now be described with reference to the drawings.
Referring first to FIG. 18, an n silicon epitaxial layer 102 is formed on a silicon substrate 101. Formed on silicon epitaxial layer 102 is a field oxide film 103 for forming an element region 102a. A polysilicon layer 104 is formed such that it covers field oxide film 103.
Referring now to FIG. 19, ion injection is employed to inject boron ions into polysilicon layer 104. The injected boron ions are held in polysilicon layer 104 at an impurity ion holding layer 105. Referring now to FIG. 20, chemical vapor deposition is employed to form an insulation layer 106 of e.g. Tetra Ethyl Ortho Silicate Glass (TEOS) on polysilicon layer 104. A predetermined photoresist pattern (not shown) is formed on insulation layer 106. The photoresist pattern is used as a mask to anisotropically etch insulation layer 106 and the polysilicon layer including impurity ion holding layer 105 so that an opening 107 is formed to expose a surface of silicon epitaxial layer 102. Thus, the polysilicon layer becomes a base extracting interconnection 4a.
Referring now to FIG. 21, heat treatment is provided to diffuse the boron ions held in impurity ion holding layer 105 into silicon epitaxial layer 102 to form an external base 105a. The heat treatment also allows formation of a silicon oxide film 108 at a side surface of opening 107 and a surface of silicon epitaxial layer 102.
Referring now to FIG. 22, insulation layer 106 is used as a mask for ion injection to inject boron ions into opening 107. The boron ions are held in silicon epitaxial layer 102 at a holding layer 109.
Referring now to FIG. 23, heat treatment is provided to diffuse the boron ions held in holding layer 109 into silicon epitaxial layer 102 to form an intrinsic base 109a.
Referring now to FIG. 24, chemical vapor deposition and the like is employed to form on insulation layer 106 a TEOS film (not shown) which fills opening 107. The TEOS film is anisotropically etched to form a sidewall 110a on a side surface of opening 107.
Referring now to FIG. 25, a polysilicon layer 111 is formed on insulation layer 106. Ion injection is employed to inject arsenic ions into polysilicon layer 111. The injected arsenic ions are held in polysilicon layer 111. Then, a predetermined photoresist pattern (not shown) is formed on polysilicon layer 111.
Referring now to FIG. 26, the photoresist pattern is used as a mask to anisotropically etch the polysilicon layer to form an emitter extracting interconnection 111a. Then, heat treatment is provided to diffuse the arsenic ions held in emitter extracting interconnection 111a into intrinsic base 109a to form an emitter 112a. The basic structure of the bipolar transistor is thus formed.
Referring now to FIG. 27, an interlayer insulating film 112 is formed to cover emitter extracting interconnection 111a and insulation layer 106. A predetermined photoresist pattern (not shown) is formed on interlayer insulating film 112. The photoresist pattern is used as a mask to anisotropically etch interlayer insulating film 112 to form an opening 113a exposing a surface of silicon epitaxial layer 102, an opening 113b exposing a surface of base extracting interconnection 104a, and an opening 113c exposing a surface of emitter extracting interconnection 111a.
Referring now to FIG. 28, an aluminum layer (not shown) is formed by e.g. sputtering on interlayer insulating film 112 to fill openings 113a, 113b and 113c. A predetermined photoresist pattern (not shown) is formed on the aluminum layer. The photoresist pattern is used as a mask to etch the aluminum layer to form a collector interconnection 114, an emitter interconnection 115 and a base interconnection 116. Thus, a semiconductor device including a bipolar transistor is thus completed.
The bipolar transistor obtained according to the manufacturing method described above, however, has the following disadvantages. External base 105a shown in FIG. 28 is formed by performing a heat treatment in the step shown in FIG. 21 to provide thermal diffusion of the boron ions held in base extracting interconnection 104a into silicon epitaxial layer 102. Thus, the boron ions are not diffused sufficient deeply into silicon epitaxial layer 102 in the vicinity of an edge of field oxide film 103. As a result, a length L of external base 105a in the vicinity of the edge of field oxide film 103 can be reduced, as shown in FIG. 29.
Furthermore, silicon epitaxial layer 102 in the vicinity of the edge of field oxide film 103 has relatively significant crystal defect and the like caused by the stress which is caused in forming field oxide film 103. Thus, there is significant crystal defect and the like in the vicinity of the junction interface between external base 105a in the vicinity of field oxide film 103 and silicon epitaxial layer 102. As a result, the breakdown voltage between external base 105a and silicon epitaxial layer 102 can be reduced, resulting in leakage of current and hence disadvantageous degradation of the electrical characteristics of the bipolar transistor.